Maintaining data integrity in DRAM while varying operating voltages

ABSTRACT

A method and apparatus for operating a DRAM while varying the supply voltage provided thereto. A memory system is designed to attach to a DRAM. The DRAM is capable of maintaining data stored therein until supply voltage is varied beyond a predetermined voltage change level without the performance of a refresh operation. The system includes a power source coupled to the DRAM for providing supply voltage thereto and a refresh signal generation device coupled to the DRAM for causing the DRAM to perform refresh operations wherein the charges associated with data bits stored within the DRAM memory cells are refreshed thereby maintaining the data integrity of data stored in the DRAM. The relative rates of supply voltage change and refresh signal provision are adjusted so as to ensure that refresh signals are provided to the DRAM prior to a point in time at which the change in supply voltage provided to the DRAM exceeds the predetermined voltage change level. Accordingly, it is possible to achieve reliable operation of the DRAM while the supply voltage provided thereto is varied.

CROSS REFERENCE TO RELATED APPLICATIONS

This application for Letters Patent is related, and cross reference maybe had to the U.S. patent application entitled "PCMCIA SRAM CardFunction Using DRAM Technology" by Scott Hadderman et al., which hasbeen assigned Ser. No. 521509 and was filed on Aug. 30, 1995 as well asthe U.S. patent application entitled "A Method for PCMCIA Card FunctionUsing DRAM Technology" by Scott Hadderman et al. which has been assignedSer. No. "521508" and was filed on Aug. 30, 1995.

FIELD OF THE INVENTION

The present invention relates to the field of memory system design forsystems in which the supply voltage levels provided to the memory may bevaried during normal operation. In particular, the present inventionrelates to a method and associated apparatus permitting the use ofdynamic random access memories (DRAM's) in systems which experiencevariations in supply voltage levels. The present invention enables thevariation of the DRAM operating voltage without Jeopardizing theintegrity of the data stored therein.

BACKGROUND OF THE INVENTION

The recent proliferation of battery-powered portable electronic dataprocessing equipment such as laptop computers, PDAs, etc, hasprecipitated a concomitant need for memory devices which offer highstorage densities and low operational power requirements. Additionally,portable memory card subsystems have been fabricated which permit a userto removably attach additional memory to their computing system. Anexample of such a memory subsystem is described in U.S. patentapplication Ser. No. 521509, filed Aug. 30, 1995 for Hadderman et al.(assigned to the present assignee hereof) which describes a PCMCIAmemory card including a DRAM device. Such removable memory subsystemsmust be capable of operation within a range of supply voltages whileensuring that the data stored in the memory device is not affected byvariations in the voltage supplied to the device. For high storagecapacity applications DRAM devices are preferred over static randomaccess memory (SRAM) devices as they typically exhibit greater storagecapacity. However, DRAM devices are typically not utilized inapplications which experience operating voltage variations, due toconcerns with data corruption or loss.

A DRAM requires a data retention mode of operation to ensure that datastored in the capacitors of each memory cell is not lost due to leakageof the capacitor or by leakage current from the substrate over time.During this data retention mode of operation, a refresh operation isperformed wherein voltage is applied to each of the memory cellcapacitors in the DRAM thereby enabling them to maintain their charge.Additionally, during normal operation modes a DRAM may receive externalrefresh instructions (i.e. ordered signals on the RAS and CAS lines ofthe DRAM) which will cause the DRAM to cycle through a refresh operationto maintain the integrity of the data stored therein.

A typical DRAM device includes a number of reference voltage cells. Eachof the memory cells in a DRAM is associated with a reference voltagecell. A sense amplifier is further associated with each memory cell forproviding access to the memory cell data. The sense amplifier amplifiesthe voltage difference between two bit lines connected to the memorycell as a bit line pair. Both lines in the bit line pair are initiallycharged to a reference voltage level V_(ref) by the associated referencevoltage cell. A memory cell capacitor containing a charge correspondingto the data stored in the particular memory cells is coupled to one ofthe lines in the bit line pair. The voltage difference between thememory cell capacitor and the coupled bit line results in either avoltage gain or a voltage drop on the coupled bit line. Accordingly, avoltage difference will develop between each line of the bit line pair.It is this voltage difference, amplified by the sense amplifier, thatrepresents the data that is stored in the particular memory cell.

The reference voltage cell charge and the charge stored in the memorycell capacitor are both restored during the refresh operation. Thevoltage level to which each of these elements are restored is a functionof the supply voltage provided to the DRAM during the refresh operation.In applications where the supply voltage provided to the DRAM variesbeyond a certain voltage level before a refresh operation occurs, thereliability of the data stored in the memory cell is questionable.

For example, assume that for a particular DRAM, the supply voltage isinitially at 5 volts and that during a refresh operation the referencevoltage cell associated with a particular memory cell is charged to 2.5volts. In an application where the supply voltage provided to a DRAMfalls from 5 volts to 2.4 volts prior to a subsequent refresh operation,a write operation, in which it is intended to write a logical 1 into theparticular memory cell may store 2.4 volts in the memory cell capacitor.At this point the V_(ref) level is still 2.5 volts which is greater thanthe charge in the memory cell capacitor (2.4 volts) precipitating thestorage of a logical 0 in that memory cell rather than the intendedstorage of a logical 1 therein.

It is apparent from the foregoing that in order to reliably operate aDRAM in a memory system which experiences significant variation insupply voltage, a mechanism must be provided to ensure that a refreshoperation is performed for each of the reference voltage cells and eachof the memory cell capacitors before the supply voltage variation cancause the loss of data integrity for the DRAM.

Presently, several designs exist which permit a DRAM to internallyprovide the required refresh operations. For example, U.S. Pat. No.4,943,960 issued Jul. 24, 1990 to Komatsu et al. for "Self Refreshing OfDynamic Random Access Memory Device And Operating Method Therefor"provides a DRAM which is capable of performing a selective refreshoperation at one of two discrete rates in accordance with a one of twoselective precharge voltage levels generated by precharge circuitrywithin the DRAM. Additionally, U.S. Pat. No. 5,365,487 issued Nov. 15,1994 to Patel et al. for "DRAM Power Management With Self-Refresh",describes a DRAM configured to perform a self-initiated refreshoperation in which on-chip power management circuits implement a specialsleep-mode self refresh process that turns certain refresh circuits onand off thereby reducing DRAM power consumption during sleep mode. U.S.Pat. No. 5,278,797 issued Jan. 11, 1994 to Jeon et al. for"Semiconductor Memory Device Capable Of Executing Non-PeriodicRefreshing Operations", describes a semiconductor memory device providedwith an internal refresh request signal generator which providesnon-periodic refresh operations within the device dependant upon thetemperature of the device. Each of the above-referenced patents,describes on-chip modification to a memory device to achieve low powerconsumption. Such customized DRAMs typically comprise expensive andinflexible designs. Furthermore, none of these inventions address theproblem of operating a DRAM while the supply voltage provided thereto isvaried.

U.S. Pat. No. 5,418,747 issued on May 23, 1995 to Tobita for a "DynamicRandom Access Memory Having A Plurality Of Rated Operating Voltages AsOperating Supply Voltage And Operating Method Thereof" describes a DRAMwhich includes on-chip circuitry capable of recognizing one of aplurality of discrete supply voltages received by the DRAM andgenerating a control signal for changing the activation timing and/orthe operating speed of the DRAM's sense amplifier in conjunction withthe supply voltage so as to operate the sense amplifier at the definedoperation speed and timing. This selective speed/timing control of thesense amplifier permits the sensitivity of the sense amplifier to beraised by decreasing the charge/discharge speed thereof, andaccordingly, the DRAM will function reliably at a lowered supplyvoltage. However, this patent requires on-chip modification to the DRAMand furthermore does not address the problem of operation of the DRAM asthe supply voltage is varied, but rather addresses the fabrication of aDRAM which is operable at plural, discrete rated operation supplyvoltages.

Consequently, the problem of operating a DRAM while a supply voltageprovided thereto is varied has not been addressed in the prior art.

SUMMARY OF THE INVENTION

The foregoing problems and the shortcomings of the prior art areovercome and additional advantages are provided by the presentinvention: a method and apparatus for maintaining the data integrity ofdata stored in a DRAM while varying the operating voltage providedthereto.

The present invention capitalizes on the property of DRAMs which permitsa given DRAM to tolerate a certain level of supply voltage varianceprior to the receipt of a refresh operation without loss of the datastored therein. The invention is premised on the principle that theadjustment of the relative rates of supply voltage change and refreshsignal provision to the DRAM will ensure that a DRAM receives aninstruction to cycle through a refresh operation prior to experiencing achange in supply voltage level which might result in the loss of DRAMdata.

A memory system according to the present invention is designed forattaching to a DRAM. A DRAM for use with the invention is capable ofperforming a refresh operation to maintain the data stored therein. Athreshold for this DRAM, may be determined, corresponding to the levelof variance in supply voltage that may be tolerated thereby in theabsence of a refresh operation without the risk of data loss. A powersource is coupled to the DRAM for providing a variable level of supplyvoltage thereto, and a refresh signal generator is coupled to the DRAMfor providing refresh signals to the DRAM to initiate the performance ofthe refresh operation.

In the present invention the rate of change of the supply voltage levelprovided through the power source to the DRAM and/or the rate of refreshsignal provision to the DRAM may be variable. The relative rates of thepower source and refresh generator are adjusted so as to ensure that theDRAM receives a refresh signal prior to a change in the supply voltagelevel that exceeds the determined threshold corresponding to thepotential for data loss. The adjustment of the relative rates may, inparticular embodiments, may entail altering the rate of the supplyvoltage change, altering the rate of the provision of refresh signals tothe DRAM or adjusting both rates.

In a first implementation of the invention, the adjustment of therelative rates may be performed in a static manner, wherein, forexample, in a first embodiment, a maximum rate of voltage change for thepower source is ascertained and the refresh signal generator isimplemented to provide refresh signals at a rate commensurate with thedetermined maximum voltage change rate. Likewise, in another embodiment,a minimum refresh signal provision rate may be ascertained and the powersource may be set to vary the supply voltage at a rate commensurate withthe ascertained minimum refresh rate. In each of these instances therelative rates of voltage change and refresh signal provision ensurethat the DRAM performs a refresh operation prior to a supply voltagevariation which may result in data loss.

In another embodiment of the invention which implements theaforementioned static adjustment of the relative rates, the DRAM mayinternally initiate the refresh operation at a set frequency. Thisinternal refresh may occur in instances such as when the DRAM device isoperating in a sleep (data-retention) mode. The static adjustment of therelative rates of the refresh signal and voltage change may beaccomplished by inhibiting the function of the refresh generator andadjusting the power source to permit the supply voltage to vary at ratecommensurate with the ascertained set internal refresh rate of the DRAM.

In a second implementation of the invention, the adjustment of therelative rates may be performed dynamically wherein the power source andrefresh signal generator are coupled to each other to communicate rateinformation therebetween. In an illustrative embodiment, the powersource may include sampling circuitry for sampling the refresh rate ofthe refresh signal generator and circuitry responsive to the sampledrate for adjusting the voltage change rate in accordance therewith.Likewise, in another embodiment, the refresh signal generator mayinclude sampling circuitry for sampling the supply voltage change ratefrom the power source and circuitry for adjusting its refresh signalprovision rate in accordance therewith. Moreover, the dynamic systemimplementation may further provide means for detecting that the DRAM hasinitiated a self-refresh operation at a fixed rate, as would be the caseduring a data-retention mode of operation, and respond by inhibiting therefresh signal generator and varying the rate of supply voltage changefrom the power source to coincide with the detected self-refreshoperation rate.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter which is regarded as the invention is particularlypointed out and distinctly claimed at the conclusion of thespecification. The foregoing and other features and advantages of theinvention will be apparent from the following detailed description inconjunction with the accompanying drawings, in which:

FIG. 1 depicts a circuit-level configuration for a typical DRAM memorycell and associated circuitry;

FIG. 2 depicts a block diagram of a memory system designed according tothe principles of the present invention;

FIG. 3 depicts a flow diagram detailing the requisite steps forimplementing a number of embodiments of the present inventive memorysystem;

FIG. 4 depicts a block diagram of the memory system wherein the variablerefresh rate is dependant upon the voltage variation rate;

FIG. 5 depicts a detailed diagram of an exemplary sense circuit for usein memory system 400, for providing a voltage variation monitorinterface between the power source and the refresh unit;

FIG. 6 depicts a block diagram of the memory system wherein the voltagevariation rate is dependant upon the variable refresh rate.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION

In accordance with the principles of the invention, a method andapparatus for maintaining the data integrity of data stored in a DRAMwhile varying its operating voltage is herein described.

Before referring in detail to our present invention, it may first beuseful to discuss, by way of example, the operation of a typical DRAMdevice, and to illustrate the problems inherent in operating a DRAM inan application wherein the supply voltage provided thereto may bevaried. Once we have provided this background, we will describepreferred embodiments of our present invention, which advantageouslyenables the use of a DRAM in such an application environment.

A conventional DRAM memory device is typically comprised of an array ofmemory cells, each of which may be independently accessed for readingand writing data thereto. Address signals are provided to the DRAM foraccessing a particular memory cell involved in a read or writeoperation. The DRAM further includes row and column decoders fordecoding the address signal to provide access to the desired memorycell. Each memory cell is coupled to a sense amplifier for reading andamplifying the data stored in the memory cell. I/O buffers are providedfor storing the data to be received by or supplied from the DRAM.

FIG. 1 depicts a circuit-level configuration for a typical DRAM memorycell. The memory cell 100 is shown connected between a bit line 101 anda word line 103. The memory cell 100 includes a memory cell capacitor104 which is coupled to the first bit line 101 through select transistor105. Select transistor 105, an n-channel transistor is turned onresponsive to a word line driving signal on word line 103 coupling it tothe memory cell capacitor.

A precharge equalizing circuit 106 includes n-FETs (107₀ -107₂).N-channel FET 107₀ is turned on via a precharge signal P applied to line108 to transmit a precharge voltage V_(pre) to the first bit line 101.The n-channel FET 107₁ is turned on in response to an precharge signal Pon line 108 to transmit the precharge voltage V_(pre) to the second bitline 102 the n-channel FET 107₂ is turned on by the equalization signalE on line 109₁ and shorts the first 101 and second 102 bit lines.Accordingly, the equalization signal equalizes the charge on the firstand second bit lines.

A sense amplifier 110 includes a CMOS flip flop connecting the first andsecond bit lines (101 and 102). The flip flop includes a pair ofp-channel FETs (111 and 112) having their gates and a first of theirelectrodes cross-coupled and a pair of n-channel FETs (113 and 114)having their gates and a first of their electrodes cross-coupled. Thefirst p-FET 111 and the first n-FET 113 are connected to the first bitline 101 via a first of their electrodes and the first of the electrodesof the second p-FET 112 and second n-FET 114 are connected to the secondbit line 102. The other electrodes of the p-FETs are connected to theline 115 upon which a first sense amplifier activating signal is drivenand the other electrodes of the n-FETS are coupled to line 116 fordriving a second sense amplifier activating signal. The CMOS flip flopis connected between supply voltage V_(cc) and ground via p-FET 117which receives a first sense amplifier activating signal 118 and n-FET119 which receives a second sense amplifier activating signal 124.

The I/O gate 123 comprises a series of n-FETs (120-122) which prechargeand equalize the potentials on lines 115 and 116 to a predeterminedpotential V_(pre) n-FET 120 is turned on in response to the signaltransmitted via line 109 and in turn transmits V_(pre) to line 115. Then-Fet 121 is likewise turned on responsive to the signal on line 109 totransmit V_(pre) to line 115. The n-FET 122 is turned on is also turnedon in response to the precharge signal on line 109 to short thepotential between lines 115 and 116 so as to equalize the potential onthese lines.

In operation, an equalization signal is applied to line 109₁ and aprecharge signal is applied to line 109. Via operation of the prechargeequalization circuit, the bit lines 101 and 102 are brought to equalpotentials typically V_(cc) /2. After a notRAS signal falls to its lowlevel, the word line signal on word line 103 rises to a high level toturn on the select transistor 105 in the memory cell 101. In response tothe select transistor 105 turning on, the memory cell capacitor 104which is at a potential other than V_(cc) /2 either charges, drawingvoltage from the first bit line 101 or discharges, slightly raising thepotential of the first bit line 101, depending upon the current state ofcharge in the memory cell capacitor 104. In either case, there iscreated a slight potential difference between the first and second bitlines 101 and 102.

Typically, at this point the sense amplifier activation signals 118 and120 drive the sense amplifier 110 into operation. The sense amplifier110 amplifies the small potential difference between the first 101 andsecond 102 bit lines and the amplified signal is transferred throughoperation of the I/O circuit to the I/O for the memory cell.

The refresh operation is similar to the above-described read operation,with the exception that the amplified data signal is not applied to theI/O line. Instead it is applied back to the memory cell capacitor 104.

From the foregoing description, it will be apparent to one of skill inthe art that a change in the supply voltage, which in turn alters thecharge on the first and second bit lines 101 and 102 may offset thedifference in potential between the first bit line 101 and the memorycell capacitor 104. Thus, if the potential on the first bit line 101 isoriginally above the potential for the memory cell capacitor 104corresponding to the storage of a logical zero in the memory cell 101,and a change in V_(cc) causes the potential on the first bit line 101 tobe lowered below the charge on the memory cell capacitor 104, the senseamplifier 110 will amplify a logical one state for the memory cell 101causing the transmission of corrupted data therefrom.

Moreover, it will further be apparent to those of skill in the relevantart, that the performance of a refresh operation maintains the correctpotential difference between the first bit line 101 and the memory cellcapacitor 104. It therefore follows that the integrity of the datastored within memory cell 100 may be accurately maintained while supplyvoltage V_(cc) is being varied, by performing the refresh operation withsufficient frequency so as to prevent the creation of an incorrectpotential difference between the first bit line 101 and the memory cellcapacitor 104. It is a principle of the present invention thatmaintenance of this correct potential difference may be achieved bycreating an association between the rate of change of supply voltageprovided to the DRAM and the rate at which refresh signals instructingthe DRAM to perform the refresh operation are provided thereto.

Turning now to our invention in greater detail, reference may be had toFIG. 2, wherein a block diagram of an exemplary memory system 200generally designed in accordance with the principles of the invention isillustrated. The exemplary memory system 200 includes a power sourceelement 201, which serves to couple a supply voltage to the DRAM 202.The power source may receive the supply voltage from any number ofcommon power supply sources. Without loss of generality, FIG. 2 depictsthe power source element 201 coupling, via a switching circuit 203,either a supply voltage from a host computer system 204 or a supplyvoltage from a battery 205 included in the memory subsystem to the DRAM202. In the illustrated embodiment, the memory subsystem 200 may beincluded on a card such as a PCMCIA card which is intended for removableinsertion into a host computer system. Such an application is discussedin U.S. patent application Ser. No. 521509 filed on Aug. 30, 1995 forHadderman et al. (commonly owned by the present assignee). In such anembodiment, the power source 201 may, for example, switch the supplyvoltage for the DRAM 202 from the host computer supply voltage 204 tothe battery-based supply voltage 205 when the memory subsystem 200 isremoved from the host computer. However, for purposes of the presentinvention it is only necessary that the level of the supply voltageprovided through the power source element 201 to the DRAM 202 is capableof variation by any means including without limitation voltagefluctuation from a single power supply as well as the removableattachment of the system to plural differently rated power supplies.

A DRAM controller including a refresh signal generator 206 is showncoupled to DRAM 202. The refresh signal generator provides a refreshsignal to the DRAM 202 which causes the DRAM 202 to initiate a refreshcycle to maintain the voltage level stored in the memory cell capacitorsand voltage reference cells within the DRAM 202. It is sufficient forpurposes of the present invention merely to understand that a refreshoperation must be performed periodically in order to maintain the dataintegrity of the data stored in the DRAM 202 and that a variation in thelevel of supply voltage provided by the power source 201 to the DRAM 202may, if it exceeds a determinable level, and is not accompanied by acorresponding refresh signal, result in corruption of the data stored inthe DRAM 202.

In order to ensure that data integrity is maintained within theexemplary memory system 200, the present invention comprises aninventive apparatus and associated techniques for establishing arelationship between the DRAM refresh rate and the supply voltagevariation rate which will allow the DRAM to maintain data integrityduring variation in either supply voltage or refresh signal rate. In afirst embodiment, the invention entails the operation of the memorysystem 200 at either a constant refresh rate or a constant supplyvoltage change rate or the determination of a minimum refresh rate or amaximum supply voltage change rate which is then treated as a constantrate, such that the corresponding supply voltage change rate or refreshsignal variation rate may be fixed to ensure that the DRAM data is notaffected. In this first embodiment it is to be understood that theinvention entails determining a first threshold rate, which may beeither the constant or maximum voltage supply rate of the power supplyor the constant or minimum rate of refresh signal generation, andthereafter establishing a second threshold rate In accordance with thedetermined first threshold rate. The second threshold rate will be theminimum established rate of refresh signal generation where the firstthreshold rate is the constant or maximum supply rate and the secondthreshold rate will be the maximum established rate of supply voltagechange from the power source where the first threshold rate is theconstant or minimum rate of refresh signal generation. In a secondembodiment, the invention contemplates variable rates of both refreshand voltage variation with the refresh rate dependent on voltagevariation rate. A third embodiment includes variable rates of bothrefresh and voltage variation with the voltage variation rate dependenton refresh rate. Each of these three preferred embodiments will beconsidered in turn.

The first embodiment, in which either the refresh rate or the rate ofvoltage variation may be held constant or the determined maximum rate ofvoltage variation or minimum refresh rate may be treated as beingconstant can be further partitioned into two counterpart embodiments:operation of the memory system 200 at a constant refresh rate or at aminimum refresh rate which in turn dictates the design of a power source201 which operates at or below a maximum voltage variation rate; andoperation of the memory system 200 at a fixed voltage variation rate ormaximum voltage variation rate which dictates the design of a refreshsignal generator (typically included in a DRAM controller) 206 whichoperates at or above a minimum refresh rate.

For illustrative purposes, consider the embodiment in which the memorysystem 200 includes a DRAM controller 206 which is to be operated at aconstant refresh rate R_(constant). From the foregoing generaldescription, it is to be understood herein that the constant refreshrate may, in actuality, either be the fixed rate R_(constant) at whichrefresh signals are provided by the DRAM controller 206 or, in anembodiment in which the refresh rate is not fixed, the valueR_(constant) may be assigned to the minimum determined refresh rate forthe DRAM controller 206 R_(min) which, for purposes of the memory system200 design is treated as a constant refresh rate R_(constant). Theconstant refresh rate R_(constant) set by the controller in combinationwith the DRAM 202 timing properties for retaining data stored therein,necessarily limit the maximum rate at which the DRAM's supply voltagemay change (dV/dt_(max)) through the power source 201. Once cognizant ofthis maximum limit, the designer must design a variable power sourcesystem 201 which will prevent the DRAM supply voltage variation ratefrom exceeding the maximum limit (dV/dt_(max)) set by the constantrefresh rate R_(constant) of the DRAM controller 206.

The above-described illustrative design may prove useful in memorysystems 200 that have already been designed around specific DRAMcontrollers 206 and specific chip sets. A power up--power down featuremay be implemented for such a memory system 200 by first determining themaximum voltage variation rate dV/dt_(max) based on the constant refreshrate R_(constant) of the memory system 200 and then designing a variablepower source unit 201 which cannot exceed the maximum rate of voltagevariation dV/dt_(max) thereby permitting the DRAM 202 to be powered upor powered down at a rate which never exceeds dV/dt_(max), which in turnensures the integrity of data stored in the DRAM 202 during such a powerup or power down operation.

As an example of a memory system 200 designed in accordance with theabove-described parameters, consider a system containing a DRAM 202which utilizes a 12/8 addressing scheme. The 12/8 addressing scheme is acommon addressing scheme for DRAMs wherein the number 12 designates 12row address bits and the number 8 designates 8 column address bits. TheDRAM 202, therefore, contains 2¹² or 4096 row addresses and a total of2.sup.(12+8) or 1M (1,048,576) address locations. Furthermore, assumefor example, that the entire row address range including all of the 4096row addresses is refreshed in sequential order at a constant rate (oralternatively at a minimum rate) (R_(constant)) of 15.6 us/cell.Finally, assume for purposes of this example, that the cell voltagevariation tolerance for the DRAM 202 is 300 mv. From this exemplaryinformation, it is possible to calculate the maximum rate of voltagechange dV/dt_(max) which will not adversely affect the integrity of datastored within the cells of the DRAM 202.

In order to calculate dV/dt_(max) for the exemplary power source 201which provides the supply voltage to the DRAM 202, it is first necessaryto calculate the total time between refresh strobes for a given rowaddress in the DRAM 202. Since the refresh rate R_(constant) has beenestablished as 15.6 us/row and since there are 4096 rows of cells in theDRAM 202 it follows that: 15.6 us/row * 4096 rows=63.8 ms. Thus, theelapsed time between sequential refresh strobes for any given rowaddress for the DRAM 202 is approximately 64 ms. Using the determinedduration between refresh cycles, the maximum allowable voltage variationdV/dt_(max) for the power source 201 which provides supply voltage tothe DRAM 202 may be determined. Since the maximum cell voltage variationtolerance for the DRAM 202 is 300 mv, it follows that: 300 mV/64ms=4.68V/s (maximum). Thus, the maximum rate at which the supply voltagemay be allowed to vary through the power source 201 in order to ensurethe integrity of the data stored in the cells of DRAM 202 is 4.68V/s.Accordingly, the power source 201 must be designed in such a manner thatit provides voltage to the DRAM 202 wherein the maximum rate of voltagevariation supplied to the DRAM 202 never exceeds 4.68 V/s. Such a powersource would typically comprise circuitry for monitoring an inputreference voltage V_(ref). The monitored input reference voltage may beutilized by the power source to set the level of the supply voltagesupplied to the DRAM 202. Thus, the rate of the variation of V_(ref)controls the supply voltage variation rate dV/dt. Having previouslydetermined dV/dt_(max) for the memory system 200, it is possible, viavarious techniques well known to those skilled in the art, includingwithout limitation the implementation of a resistor capacitor networkcoupled to a reference voltage generator, to limit the variation rate ofthe reference voltage V_(ref) to be within the slew rate defined bydV/dt_(max).

A DRAM 202 which includes self-refresh circuitry, may also be used asdescribed above. The self-refresh circuitry will have an associatedrefresh rate. This pre-set refresh rate will necessitate a maximumvoltage variation rate for the power source 201 in a similar manner aswas described above for R_(constant) for the DRAM controller 206. Amemory system 200 may further be designed so as to permit a DRAM 202 toenter a self-refresh mode after which the supply voltage providedthereto is reduced, this implementation would further reduce the powerconsumption of the memory system 200. In such a memory system the powersource circuit 201 would be designed so that the maximum rate of voltagevariation will allow for data retention in accordance with theself-refresh rate of the DRAM 201. Such a memory system design mayentail the inclusion of refresh signal inhibit logic within the DRAMcontroller 206 actuated by a signal from the host indicating that theDRAM 202 is to be placed in self-refresh mode, which in turn causes theDRAM controller 206 to place the DRAM 202 into its self-refresh modeand, via the refresh signal inhibit logic, to inhibit the generation ofrefresh signals therefrom when the DRAM 202 has entered its self refreshmode. Memory system designs incorporating such a feature are well knownto those skilled in the pertinent art, and as such, a detailedexplanation of an exemplary design is not required for an understandingof the present invention. In such a system, it would also be necessaryto consider the refresh rate of the DRAM 202 in its self-refresh modewhen determining the minimum refresh rate which establishes dV/dt_(max).In an alternative design, the power source 201 may include means forswitching between two different maximum voltage slew thresholds(dV/dt_(max)) depending upon whether the refresh signals are beingprovided from the DRAM controller 206 or from the DRAM 202 inself-refresh mode.

The counterpart embodiment of the first example is a memory system 200in which the power source 201 provides a supply voltage at a constantvoltage variation rate, or at a maximum voltage variation rate which isto be treated as a constant (dV/dt_(constant)). In this example, theproper refresh rate R_(min) to compensate for this determined voltagevariation rate must be calculated. The DRAM controller 206 whichprovides the refresh signal to the DRAM 202 may be designed such that italways maintains a rate of provision of the refresh signals at or abovethe refresh rate R_(min) dictated by the constant voltage variation ratedV/dt_(constant). This embodiment would prove useful for applications inwhich the memory system 200 experiences large variations in supplyvoltage. The use of a DRAM 202 in such applications has typically beenavoided as a consequence of the foregoing DRAM data integrity problemsassociated with voltage variation. Using the determined maximum rate ofsupply voltage variation dV/dt_(max) which is treated as a constantdV/dt_(constant), a minimum refresh rate R_(min) may be calculated forthe refresh signal from the DRAM controller 206 which will permit theDRAM 202 to maintain data integrity even when the voltage variation rateis at its maximum, thus allowing such a DRAM 202 to be used in systemswith large variations in supply voltage.

As an example, consider the DRAM parameters described in the previousexample, which comprised a DRAM 202 having a 12/8 addressing scheme with4096 row addresses which are sequentially refreshed, and which have acell voltage variation tolerance of 300 mV. In the present example thereexists a determined maximum variation dV/dt_(max) in the supply voltageprovided via the power source 201 to the DRAM 202. For illustrativepurposes, assume that this determined maximum supply voltage variationwhich is to be treated as being constant dV/dt_(constant) is 3V/s.

From this determined maximum supply voltage variation rate it ispossible to calculate the minimum required refresh rate R_(min) at whichthe DRAM controller 206 must be configured in order to provide refreshsignals so as to maintain the integrity of the data stored in the DRAM202. Initially, it is possible to determine that it will take 100 ms forthe voltage to vary to the voltage variation tolerance level 300 mV viathe following calculation: 300 mV * 1/(3V/s)=100 ms. Using thedetermined 100 ms time period associated with the 300 mV voltagevariation tolerance it is possible to ascertain the minimum refresh rateR_(min) that is required to ensure that a given row of cells in the DRAM202 is refreshed before the voltage supplied to that row has varied bymore than 300 mv via the following calculation: 100 ms/4096 rows=24.4us. Thus, in order to ensure data integrity in the illustrative memorysystem 200, the DRAM controller 206 must be configured to ensure thateach row in the DRAM 202 will receive a refresh strobe at least every24.4 us. A typical DRAM controller 206 for such a memory system 200 isimplemented in a programmable logic device ("PLD") such as a gate arrayor an application specific integrated circuit ("ASIC"), and as such theconfiguration of the refresh rate to ensure compliance with R_(min) maybe achieved via the logic design of the PLD, however it is alsopossible, and specifically contemplated herein, that various otherdesign techniques may be employed to so-configure the DRAM controller206.

Referring to FIG. 3, an illustrative flow diagram details, inter-alia,the design steps required for the above-described counterpart firstembodiment memory systems. If it is desired to implement a static memorysystem 301 in which one of the refresh signal rate or the supply voltagechange rate will be treated as being constant, the first step entailsthe determination of the constant rate 302. As previously described, theconstant rate or so-called first threshhold rate may, in realityrepresent a determined maximum supply voltage change rate dV/dt_(max)which is treated as a constant for purposes of the design, or likewise,it may entail the determination of a minimum refresh signal rate R_(min)which will be treated as a constant for purposes of the design. Ineither case, the next step includes the derivation of a refresh signalor supply voltage change rate 303 corresponding to the previouslydetermined 302 supply voltage change or refresh rate respectively, suchthat the DRAM will perform a refresh operation preserving the integrityof the data stored therein prior to experiencing a supply voltage changewhich might result in corrupted data. Finally, after the correspondingso-called second threshhold rate has been derived 303, the DRAMcontroller 206 or the power source 201 is implemented 304 such that itadheres to its previously derived rate.

Turning now to the second embodiment of the invention, a memory system400, as illustrated in FIG. 4, may be implemented in which both therefresh rate and the voltage variation rate are variable, and in whichthe refresh rate is dependent on the voltage variation rate. In such amemory system 400, a voltage supply power source 401 supplies thevariable rate supply voltage to the DRAM 402. The DRAM controller 406typically includes a refresh unit 407, which can refresh the DRAM 402 atvariable frequencies and which may be implemented such that the refreshsignal rate is synchronous with the frequency of the input signal(hereinafter a sense signal) received thereby. This refresh unit 407must be able to refresh the DRAM at rates which ensure the integrity ofthe data stored in the DRAM 402 even at times when the rate of supplyvoltage variation is maximized.

In order to establish this association between the variable refresh rateand the variable supply voltage rate, an interface voltage rate detector408 between the DRAM refresh unit 407 and the DRAM voltage supply powersource 401 is implemented so as to enable the refresh unit 407 toeffectively monitor the rate of DRAM supply voltage change through thepower source 401. The voltage rate detector 408 permits the definitionof the correspondence between the refresh rate and the voltage variationrate such that, as the rate of supply voltage variation increases, therefresh rate will increase and as the rate of supply voltage variationdecreases, the refresh rate will decrease.

The mechanism included in the voltage rate detector 408, for monitoringthe voltage variation rate may be achieved via a variety ofimplementations. In an illustrative embodiment, and without loss ofgenerality, the interface may comprise a voltage variation sense circuit500 which couples the voltage supplied via the power source 401 tothrough a counter 409 to the refresh unit 407. The illustrative sensecircuit 500, depicted in detail in FIG. 5, may, in an embodiment of theinvention, be simply implemented via resistor 501 and capacitor 502coupled in series, and in turn coupling the DRAM supply voltage signalfrom the power source 401 to the refresh unit 407. When there is novariation in the DRAM supply voltage which serves as input voltage 503to the sense circuit 500, the output voltage 504 across the resistor 501which is subsequently provided to the refresh unit 407 is 0v. As theinput voltage 503 varies, the output voltage 504 subsequently providedto the refresh unit 407, will vary in proportion to the rate of theinput voltage variation. This voltage variation, in turn, controls therate for the refresh signal generated by the refresh unit 407.

The sense circuit 500 and the refresh unit 407 may be coupled to oneanother in the illustrative embodiment via a voltage controlledoscillator (VCO) 506 and counter 409. The VCO 506 is designed such thatits output signal (or sense signal) 508 frequency which is an input forcounter 409, is proportional to the absolute value of the input voltage503. As the magnitude of the output voltage 504 increases, implying anincrease in the rate of supply voltage variation to the DRAM 402, theVCO 506 produces an output signal (or sense signal) 508 with acorrespondingly increased frequency, which will in turn cause thecounter 409 to increment its count at an augmented rate. The counter 409may be configured to count up to a predetermined value before emitting arefresh generate signal 410 to the refresh unit 407. It thereforefollows, that as the supply voltage variation rate increases, thefrequency of the refresh generate signal 410 and corresponding therefresh signal rate from the refresh unit 407 will increase.Furthermore, from the foregoing description it will be readilyunderstood by those skilled in the relevant art that a decrease in theDRAM supply voltage variation rate will correspondingly diminish themagnitude of the sense signal 508, which will correspondingly result ina decrease in the rate at which the refresh signal is provided from therefresh unit 407 to the DRAM 402.

Advantageously, memory systems 400 in which the refresh rate may vary toaccommodate supply voltage variation rates need not operate at apre-determined maximum refresh rate as would memory systems 200 designedin accordance with the first embodiment of the invention. In thevariable refresh rate memory system 400, the refresh rate can be slowedwhen the supply voltage variation rate slows which in turn increases theaccess availability of the DRAM 402, and accordingly reduces the powerconsumed as well as the heat produced by the DRAM 402.

Referring again to the flow diagram of FIG. 3 it can be seen that wherea dynamic memory system 400 wherein the refresh rate is dependent uponthe supply voltage change rate 305 is designed, the first step entailsthe determination of the current supply voltage change rate 306. Upondetermining the current supply voltage change rate, the requisiteminimum current refresh signal rate which will ensure that the DRAM 402is refreshed prior to a change in the DRAM supply voltage which couldcorrupt the DRAM data occurs, is derived 307. Once this minimum currentrefresh rate is derived 307, the refresh signal generator portion of theDRAM controller 406 is adjusted to provide refresh signals to the DRAM402 at or above the derived minimum refresh rate 308. The abovedescribed steps 306-308 are constantly repeated 309 so as to sample thenew current supply voltage change rate.

Turning now to a third embodiment of the invention, a memory system suchas the memory system 600 depicted in FIG. 6 may be implemented in whichboth the refresh rate and the voltage variation rate are variable and inwhich the voltage variation rate is dependent upon the refresh rate. Insuch a memory system 600, a voltage supply power source 601 may bedesigned to provide the DRAM supply voltage to the DRAM 602 at differentrates of voltage variation dV/dt. A refresh unit 607 also exists,usually as part of a DRAM controller 606, which provides refresh signalsto the DRAM 602 for refreshing the data stored therein. The illustrativeDRAM controller 606, through the refresh unit 607 may generate theserefresh signals at variable frequencies thereby refreshing the DRAM 602data at variable frequencies. In an illustrative embodiment of such amemory system 600, an interface or refresh rate detector 608 existsbetween the DRAM refresh unit 607 and the DRAM voltage supply powersource voltage converter 609 which enables the voltage converter 609 toeffectively monitor the rate at which the DRAM refresh signals areprovided by the refresh unit 607.

An exemplary refresh rate detector 608, includes a clock generator 611,coupled to an up/down counter 612, which is in turn coupled to a digitalto analog (D-A) converter 613 which is coupled to the voltage converter609. The clock generator 611 receives, as an input signal, the refreshsignals from the refresh unit 607, and generates an output clock pulse615 for every refresh signal received. The voltage converter component609 comprises circuitry for monitoring an input reference voltageV_(ref) 616. This reference voltage V_(ref) 616 is used by the voltageconverter 609 to set the level of the supply voltage which is suppliedto the DRAM 602. The voltage converter 609 receives a source voltagefrom an external source and monitors the reference voltage V_(ref) 616to maintain power to the DRAM 602 such that the supply voltage providedto the DRAM 602 is proportional to the input reference voltage V_(ref)616. The reference voltage V_(ref) 616 that is used by the voltageconverter 609 for provision of supply voltage to the DRAM 602 is in turngenerated by the D to A converter 613. The up/down counter 612 iscapable of counting up to a predetermined maximum count level and ofcounting down to a predetermined minimum count level. The determinationof whether the counter 612 is to count up or count down is dependantupon the then existing state of the memory system 600. In theillustrative example of such a memory system 600, the up/down counter612 receives a power up/down signal 617 from the host system, indicativeof whether the memory system 600 is currently being powered up or down.The up/down counter 612 will count up in response to power up requestsignals 617 and correspondingly the up/down counter 612 will count downin response to power down request signals 617. The up/down counter 612utilizes the clock signal 615 received from the clock generator 611 totrigger each incremented or decremented count.

During steady state operation, while the memory system 600 is neitherpowering up or powering down, the up/down counter 612 is maintained atits predetermined minimum or maximum count level. This predeterminedminimum or maximum count level is in turn provided as a digital inputsignal 620 to the D to A converter 613 where it is converted toreference voltage V_(ref) 616 which is proportional to a steady state(i.e. a power up or power down) supply voltage for the DRAM 602. Thisreference voltage V_(ref) 616 is monitored as previously described bythe voltage converter 609 which in turn provides the normal operatingsupply voltage to the DRAM 602.

Upon sensing a power up/down request signal 617 from the host system,the up/down counter 612 begins to count up or down toward itspredetermined maximum or minimum count level. The up/down counter 612will only increment or decrement, however, upon receipt of a clock pulse615 from clock generator 611. Thus, the frequency of the clock pulse615, will determine the rate at which the up/down counter 612 will countand correspondingly, the rate at which the D to A converter receives adigital signal and ultimately, the rate at which the DRAM voltage willrise to the power up level or drop to the power down level. It haspreviously been established that the frequency of the clock pulse 615 isdirectly proportional to the refresh signal frequency from the refreshunit 607. Accordingly, it will be apparent from the foregoingdescription that the refresh signal frequency will limit the slew rateof the DRAM's supply voltage.

A memory system 600 designed generally in accordance with the principlesof the illustratively depicted third embodiment of the present inventionwould prove useful in a processing system designed with a low power modeof operation. When such a processing system initiates a power down mode,for example, a signal is sent to the power source 601. Upon sensing thissignal, the power source 601 begins reducing the supply voltage providedto the DRAM 602 at a rate corresponding to the refresh rate sensed bythe refresh rate detector 608. As the supply voltage provided to theDRAM 602 decreases, the power source 601 via the refresh rate detector608, will continually monitor the refresh rate and adjust the supplyvoltage variation rate accordingly. This voltage slew continues untilthe DRAM supply voltage has reached the power down voltage level. Whenthe memory system 600 subsequently resumes normal power mode, the powerdown signal is removed and the reverse operation occurs raising the DRAMvoltage above the power down level.

Referring once again to the illustrative flow diagram of FIG. 3, adynamic memory system 600 in which the current supply voltage rate isderived from the current refresh signal rate 305, is designed by firstsampling the current refresh signal rate 309 from the refresh signalgenerator 607. The sampled current refresh signal rate is then used toderive 310 the maximum current supply voltage change rate for the powersource 601 which will ensure that the DRAM 602 is refreshed prior to theoccurrence of a change in the DRAM supply voltage which could corruptthe DRAM data. Once the maximum current supply voltage change rate forthe power source 601 has been derived the final step entails adjustingthe power source 601 to provide supply voltage to the DRAM 602 with asupply voltage change rate at or below the derived maximum currentsupply voltage change rate 311. The above described steps 310-312 areconstantly repeated thereafter 313, so as to sample the new currentrefresh rate.

In memory systems which are designed in accordance with the principalsof the second and third embodiments of the invention such as memorysystems 400 and 600, it is possible to incorporate a DRAM which includesa self-refreshing operation, in a manner similar to that described forthe exemplary embodiments characterized by memory system 200. For amemory system designed in accordance with memory system 400, theinclusion of such a feature would dictate the design of a power source401 having a maximum voltage slew rate dV/dt_(max) determined inaccordance with the specified minimum self-refresh rate R_(min) for theself-refreshing DRAM 402. Alternatively, memory system 400 may includemeans for ascertaining from a connected host system that the DRAM 402has been placed in a self-refresh mode and for adhering to the specifiedminimum self-refresh rate R_(min) for the self-refreshing DRAM 402 whilethe self-refresh operation mode persists. In memory systems typified bythe memory system 600, the power source 601 includes the refresh ratedetector 608 which, as previously described, samples the refresh ratefrom the DRAM controller 606. When the DRAM 602 in memory system 600enters self-refresh mode, the provision of refresh signals from the DRAMcontroller 606 to the DRAM 602 are inhibited in a manner similar to thatwhich has been previously described in connection with memory system200. At this point the refresh rate detector 608 will determine that norefresh signals are being sent from the DRAM controller 606 to the DRAM602 and accordingly that the DRAM has entered its self-refresh mode. Inresponse to this determination, the power source 601 will operate byproviding supply voltage to the DRAM 602 at a maximum voltage slew ratedV/dt_(max) which is commensurate with the specified minimumself-refresh rate R_(min) for the DRAM 602 to ensure that the integrityof the data stored therein in maintained.

Although preferred embodiments have been depicted and described indetail herein, it will be apparent to those skilled in the relevant art,both now and in the future, that various modifications, additions,improvements and enhancements may be made without departing from thespirit of the invention, and these are therefore considered to be withinthe scope of the invention as defined in the following claims whichshould be construed to maintain the proper protection for the inventionfirst disclosed.

Having described our invention, what we claim as new and desired tosecure by Letters Patent is as follows:
 1. In a memory system forsupporting a memory, said memory capable of performing refreshoperations to maintain a logical state for data stored therein, saidmemory system including a power source for providing supply voltage tothe memory, and a refresh signal generator for providing a refreshsignal to the memory for causing the memory to perform the refreshoperation, and wherein a predetermined level of supply voltage variationmay be experienced by the memory prior to the performance of saidrefresh operations for said data, without loss of the logical stateassociated with the data stored therein, a method for operating thememory system to permit the supply voltage to be varied beyond saidpredetermined level of supply voltage variation without loss of thelogical state associated with the data, the method comprising the stepsof:determining a first threshold rate for one of said power source andsaid refresh signal generator; establishing a second threshold rate forthe other of said power source and said refresh signal generator, saidestablished second threshold rate being derived from said determinedfirst threshold rate to ensure that the data stored in said memory hasbeen refreshed before the supply voltage provided to the memory variesbeyond said predetermined level; and designing the other of said powersource and said refresh signal generator to operate within saidestablished second threshold rate.
 2. A method according to claim 1wherein the determined first threshold rate is a maximum rate of supplyvoltage change from the power source and the established secondthreshold rate is a minimum rate of refresh signal generation from therefresh signal generator.
 3. A method according to claim 1 wherein thedetermined first threshold rate is a minimum rate of refresh signalgeneration from the refresh signal generator and the established secondthreshold rate is a maximum rate of supply voltage change from the powersource.
 4. A method according to claim 1 wherein the determined firstthreshold rate is a constant rate.
 5. A method according to claim 4wherein the determined first threshold rate is a constant rate of supplyvoltage change from the power source and the established secondthreshold rate is a minimum rate of refresh signal generation from therefresh signal generator.
 6. A method according to claim 4 wherein thedetermined first threshold rate is a constant rate of refresh signalgeneration from the refresh signal generator and the established secondthreshold rate is a maximum rate of supply voltage change from the powersource.
 7. A method according to claim 1 wherein the power sourceincludes means for connecting to a plurality of power supplies.
 8. Amethod according to claim 1 wherein the operation of said memory systemto permit the supply voltage to be varied beyond said predeterminedlevel of supply voltage variation includes powering up the memory systemfrom a powered down state.
 9. A method according to claim 1 wherein theoperation of said memory system to permit the supply voltage to bevaried beyond said predetermined level of supply voltage variationincludes powering down the memory system from a powered up state.
 10. Amethod according to claim 1 wherein the memory is a DRAM.
 11. A methodaccording to claim 10 wherein the DRAM includes a self-refresh mode ofoperation.
 12. A method according to claim 11 wherein the refresh signalgenerator includes means for inhibiting the provision of the refreshsignal therefrom if the DRAM is operating in the self-refresh mode ofoperation.
 13. A method according to claim 11 further comprising thesteps of:determining the refresh rate of the DRAM if the DRAM isoperating in the self-refresh mode of operation; establishing a supplyvoltage variation rate for said power source in accordance with saiddetermined refresh rate of the DRAM to ensure that the DRAM refreshesthe data stored therein before the supply voltage provided to the DRAMhas varied beyond the predetermined level; and adjusting the powersource to operate at said established supply voltage variation rate. 14.An apparatus for supporting a memory, said memory being capable ofperforming refresh operations to maintain a logical state for datastored therein, said memory is further being capable of experiencing apredetermined level of supply voltage change prior to the performance ofsaid refresh operations without loss of the logical state of the datastored therein, wherein said apparatus permits the supply voltage to bevaried beyond said predetermined level without the loss of the logicalstate of the data stored in the memory, the apparatus comprising:a powersource having means for coupling to said memory for providing a supplyvoltage to the memory; and a refresh signal generator having means forcoupling to said memory for providing a refresh signal to said memory tocause said memory to perform said refresh operations; and wherein afirst one of said power source and said refresh signal generatoroperates at a first threshold rate and the other of said power sourceand said refresh generator is implemented to operate within a secondthreshold rate so as to ensure that the data stored in the memory hasbeen refreshed before the supply voltage has varied beyond saidpredetermined level.
 15. An apparatus according to claim 14 wherein saidfirst threshold rate is a maximum rate of supply voltage change from thepower source and the second threshold rate is a minimum rate of refreshsignal generation from the refresh signal generator.
 16. An apparatusaccording to claim 14 wherein said first threshold rate is a minimumrate of refresh signal generation from the refresh signal generator andthe second threshold rate is a maximum rate of supply voltage changefrom the power source.
 17. An apparatus according to claim 14 whereinthe first threshold rate is a constant rate.
 18. An apparatus accordingto claim 17 wherein the first threshold rate is a constant rate ofsupply voltage change from the power source and the second thresholdrate is a minimum rate of refresh signal generation from the refreshsignal generator.
 19. A method according to claim 17 wherein the firstthreshold rate is a constant rate of refresh signal generation from therefresh signal generator and the second threshold rate is a maximum rateof supply voltage change from the power source.
 20. An apparatusaccording to claim 14 wherein the power source further includes meansfor connecting to a plurality of power supplies.
 21. An apparatusaccording to claim 14 wherein the operation of said memory system topermit the supply voltage to be varied beyond said predetermined levelof supply voltage variation includes powering up the memory system froma powered down state.
 22. An apparatus according to claim 14 wherein theoperation of said memory system to permit the supply voltage to bevaried beyond said predetermined level of supply voltage variationincludes powering down the memory system from a powered up state.
 23. Anapparatus according to claim 14 wherein the memory is a DRAM.
 24. Anapparatus according to claim 23 wherein the DRAM includes a self-refreshmode of operation.
 25. An apparatus according to claim 24 wherein therefresh signal generator further includes means for inhibiting theprovision of the refresh signal therefrom if the DRAM is operating inthe self-refresh mode of operation.
 26. An apparatus according to claim24 further comprising means for determining the refresh rate of the DRAMif the DRAM is operating in the self-refresh mode of operation;means forestablishing a supply voltage variation rate for said power source inaccordance with said determined refresh rate of the DRAM to ensure thatthe DRAM refreshes the data stored therein before the supply voltageprovided to the DRAM has varied beyond the predetermined level; andmeans for adjusting the power source to operate at said establishedsupply voltage variation rate.